In the field of digital computers, most, if not all, contemporary computer systems are built around a bus structure. All the elements are connected to the bus and all communications and transfer of data between the elements are conducted over the bus. The bus has the central processing unit (CPU) connected to it along with the random access memory (RAM) containing instructions and data as well as any peripheral devices, including input devices and output devices. In earlier computers, it was common to include a device controller in each of the peripheral devices. Such redundancy was not space- or cost-effective and, therefore, most computers in present use employ a direct memory access controller (DMAC) which controls the use of the bus for the entire system.
A typical prior art DMAC is dedicated to elementary operations on data blocks, such as copying one memory block to another, transferring data between memory and I/O devices, and comparing two memory blocks for equality. It performs such operations in one or two bus cycles per data item. These operations can be carried out by the CPU; but, they take several bus cycles per data item because of the overhead in counting loop executions and testing for completion. The use of a DMAC, therefore, gives the system a greater throughput. As is known and appreciated by those skilled in the art, this is the primary objective of such devices. Since all information (i.e., instructions, data, etc.) flows through the bus, it can become a bottleneck to the entire system proving the old adage of the "weakest link". No matter how fast the various devices can operate and perform their functions, system throughput ultimately grinds to the pace of the information transfer through the bus. Thus, optimizing bus usage is a primary system design objective.
A DMAC functions as a co-processor and bus master; that is, it takes control of the bus from the CPU when it has an operation to perform. It has its own control logic and bus drivers for reading and writing the control, address, and data lines. Since only one processor can drive the bus at a time, there must be an orderly method for transferring control between processors (i.e. the CPU and the DMAC). The HOLD/HOLDA protocol is typical of the prior art approach to this problem. When the DMAC wants the bus, it asserts the HOLD control signal (i.e., it drives it to the TRUE state). The CPU responds to HOLD by suspending operation, disconnecting most of its drivers from the bus, and asserting HOLDA (hold acknowledge) when that has been done. The CPU is idle as long as HOLD is asserted. The DMAC monitors the HOLDA signal and starts its operation when it sees the TRUE state (indicating that the CPU has come to an orderly halt and it through with the bus). When the DMAC has completed its operation, it disconnects from the bus, and de-asserts HOLD (i.e., drives it to the FALSE state). Upon seeing HOLD de-asserted, the CPU takes control of the bus once again and resumes operation.
It should be noted that typical prior art bus definitions require the CPU to give up the bus when HOLD is asserted, but they do not require the DMAC to give it back. There is, therefore, a danger that a DMAC process can keep the bus for a long time and "starve" other processes. A desirable objective in generating a DMAC specification, therefore, would be to provide some means for controlling the conditions and durations of its bus accesses. These could include a "burst" value, to determine the length of time that a process may control the bus during its current access, and a "latency" value, to determine the time that a DMA process has to wait, after releasing the bus, before its next bus access.
Typical prior art bus control chips contain four channels that execute independent processes. There is only a single bus interface for the chip, however, and, therefore, only one channel may be active at a time. Since the channel processes are independent, they compete for the bus. The chip must, therefore, include some sort of internal priority control mechanism. In the prior art, this is typically a hard-wired function. Likewise, if the system has more than one DMAC, the system itself must provide an overall priority control mechanism, such as a bus arbiter, to deal with simultaneous HOLD request from different DMAC chips.
In the prior art, there are typically two general types of DMA processes, distinguished by the way in which requests for bus access are generated. The first type is associated with asynchronous I/O operations (e.g., keyboard, printer, disk controller, etc.), the second with memory operations. An asynchronous device asserts a hardwired REQUEST signal to the channel when it has data to deliver or is ready to accept data. The channel responds by requesting bus access. When access is granted, the channel asserts ACKNOWLEDGE to the I/O device, which then reads or writes the bus. The notion of "data ready" does not apply meaningfully to memory, however--it is always ready. The decision to request bus access for a memory transfer must come from the channel itself. This second type of channel process has various names in DMA literature. For convenience only, it will be referred to as "auto-request" hereinafter.
Slow I/O devices do not need regulation of their demands on the system bus because they request service infrequently. Fast I/O devices and memory (auto-request) transfers, on the other hand, are capable of monopolizing the bus and, therefore, need some form of regulation.
In the prior art, the CPU is totally in charge of the system. It initializes the DMAC, sets up the channel processes, starts them, and handles events such as termination of a process and interrupts from a process. Such tasks are, of course, wasteful of CPU time that could be employed for computational purposes and, therefore, reduce overall system performance and throughput.
DMA processes typically involve one or two addresses. A separate bus cycle is needed for each address. Consequently, single-address processes take one bus cycle and double-address processes take two bus cycles. Advanced prior art DMA controllers provide additional functions such as comparing two memory blocks for equality and searching a memory block for a value. All may be classified as single- or double-address processes, however.